Lead RF/Analog ASIC Design Engineer

As a Lead RFIC Design Engineer you are responsible for block level design in Ku/Ka band RF Transmitters and Receivers for next generation of satellite communications in deep sub-micron technologies. You are responsible for architecture design, circuit design & verification, review for RFIC building blocks like PA, Active VGA and Phase Shifters. The job places you at the helm of ASIC development where you will develop new circuit architectures, design/verification methodologies to deliver ASICs that meet all the performance requirements in the required timeline. While the job primarily involves you to own block level designs, you will work closely with the layout engineer to ensure the layout meets all the constraints for the best silicon performance. As a Lead Engineer, you will work closely with the chip leads in block level design reviews, top level verification and with test team in developing the test plan and characterising the ASIC. Ideal candidate will have 6 years of experience in the design of RFICs and will be a design expert for one of PA, Phase Shifter, Active VGA in deep sub-micron technologies. Technical Responsibilities: Responsible for architecture and circuit design for RFIC building blocks like PA, Phase Shifter, Active VGA. Delivering high quality RF/Analog blocks with leading edge performance using innovative architectures and circuit implementations. Work closely with the layout team on IP floor-planning, trial layout design, parasitic extraction, and modifications. Co-ordinate design activities with other colleagues. Document own work and lead in design reviews. Organisational Responsibilities: Ongoing development of core competencies & technical skills Mentoring junior engineers Receptive and agile to the project needs. Good estimation of timescales for own projects & sub tasks Follow good engineering practices including processes, documentation, tools & automation. Identify risks, flag issues in a timely manner so project milestones remain on schedule. Qualifications & Skills: Essential: An Engineering degree in a relevant discipline Minimum of 6 years’ experience in RFIC Design (preferably 15GHz or higher operating frequencies) – including 2 or more successful tape-outs. Excellent understanding of state-of-the-art RF CMOS circuit design and transceiver architectures – especially PA design. Experience of designing high performance Analog/RF circuits in deep sub-micron technology as well as a strong analytical approach with a clear track record of success and delivery. Cadence Virtuoso Design Framework Experience Ability to work and interact with engineering teams across multiple disciplines during ASIC development. Great communication skills and able to take responsibility for complex circuit and system designs and delivery to tight timescales. Desirable: Experience in 22nm FDSOI or other sub 45nm CMOS process nodes for RF/High speed ICs Experience with process relating to production release and qualification. Experience in EM modelling tools such as RFPro or EMX Experience in mmW/RF IC design Understanding of Radio systems, gain and noise budgeting, phase noise and intermodulation mechanisms Experience in RFIC Characterisation Experience in Chip ESD design & qualification