Formal Verification Application Engineer

Formal Verification Application Engineer – Cambridge A market-leading EDA company is looking for an experienced Engineer to come and join their Application Engineering team in Cambridge. This is a fantastic opportunity for a Formal Verification Engineer to progress into a more customer-facing role as you will interact closely with the R&D team and the customer.In this role you will have a fantastic opportunity to expand your Formal Verification skills and work closely with a leading-edge customer!Requirements:Bachelor or Master in Electronic Engineering or a related fieldProven technical experience in Jasper Gold, OneSpin, or VC Formal is essentialKnowledge of Verilog, System Verilog or VHDLInvolved in several tapeouts at multiple technology nodesEmail - [email protected] - 01189073075LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/